Qualcomm has introduced its High Bandwidth Compute (HPC) technology, designed to address memory-bandwidth constraints in artificial intelligence data centres. The company aims to tackle the "memory wall"—a mismatch identified around 2021 between increasing compute capacity and slower memory bandwidth growth—specifically within the decode portion of AI inference workloads.

The HPC approach uses compute-and-memory co-design. While Qualcomm does not manufacture the DRAM stacks, it provides the compute die and system design, working with foundry partners including TSMC. The company targets a sixfold improvement in tokens per second per watt relative to high-bandwidth memory (HBM). Qualcomm claims its architecture can provide memory bandwidth in the "hundreds of terabytes per second", compared to approximately 21 to 22 terabytes per second for current HBM.

The rollout for HPC technology is scheduled as follows:

• 2027: Expected commercial shipping of first-generation products.
• 2028: Planned release of a second generation.

Beyond HPC, Qualcomm is expanding its data-centre presence with the Dragonfly C1000 server CPU, which Meta has been announced as the first customer for. The C1000 is scheduled for commercial availability in the second half of 2028. The company is also pursuing parallel Arm and RISC-V processor roadmaps, describing RISC-V as a parallel option rather than a replacement for Arm.

To support its AI ecosystem, Qualcomm is utilising several recent moves:

• The acquisition of Modular to support AI workloads via the Mojo programming language and MAX compiler stack.
• A partnership with Hugging Face to automate AI model onboarding for developers.
• The acquisition of Alphawave’s custom-silicon and networking assets.

"It eventually will lead to a memory wall,"

said Durga Malladi, Qualcomm's executive vice president of technology planning and edge data centre, regarding the performance constraints in AI inference.